As the feature size of devices is reduced to 22 nm node, difficulties may occur in improving operating speed of chips therein, increasing integration and decreasing costs by reducing the feature size using integrated circuit technique according to Moore's Law. With the increase of costs for nanometer process, the short channel effect degrades the control ability of gates, and factors, such as limitation of mobility of Si material itself etc., make it impossible to reduce the feature size of the device continuously. Therefore, various possible solutions are proposed constantly. A third generation Ivy Bridge processor launched in China by Intel in April 2012 utilizes a 22 nm manufacture process of a 3D tri-gate Fin-FET. Another solution is to employ Group III-V/Ge high-mobility channels.
The electron mobility of a Group III-V compound semiconductor is much higher than that of Si (e.g. the electron mobility of GaAs and InAs materials may be up to 9000 cm2V−1·s−1 and 40000 cm2V−1·s−1, respectively, while the electron mobility of Si is only 1300 cm2V−1·s−1). The Group III-V compound semiconductor may have excellent electron transport performance in either a low field or a high field, and may be an ideal channel material for nMOS of ultrahigh speed and low power consumption. At the same time, the hole mobility of Ge (1800 cm2V−1·s−1) is higher than that of Si (500 cm2V−1·s−1). It has become a focus of research in the microelectronics field to substitute the strained-Si material for channel with the high-mobility Group III-V semiconductor material and Ge material compatible with Si processes so as to significantly improve the switch speed of logic circuits and to achieve low power consumption.
A precondition for manufacturing a Si-based high-mobility CMOS device with a large area and low costs is epitaxial growth of high-quality Group III-V semi-conductor material and Ge material on a Si substrate. Epitaxial growth of Si-based Ge material and devices thereon are always important research topics in micro-electronics and photo-electronics field. UHVCVD may be used for obtaining a Ge layer with a high quality and flat surface. On the other hand, GaAs is a relative mature Group III-V semiconductor material, but epitaxial growth of Si-based GaAs may encounter many problems. There are a substantial lattice mismatch (4.1%) and a substantial thermal mismatch (thermal expansion coefficients of Si and GaAs are 2.59×10−6K−1 and 5.75×10−6K−1, respectively) between Si and GaAs. Therefore, a great amount of dislocations will occur during heteroepitaxial growth. Also, a great deal of APDs (Anti-phase domains) may be generated in an epitaxial layer during epitaxial growth of a polar material on a non-polar substrate. The APDs may also be generated due to existence of substrate steps. An APB (Anti-phase boundary) is a scattering and recombination center of carriers, which may introduce a defect level in a forbidden band. These dislocations and APBs may extend to a surface of the epitaxial layer, which will substantially affect quality of the epitaxial layer. Typically, a Ge layer is grown as a transition layer before growth of the Si-based Group III-V semi-conductor material. Then a high-quality Group III-V layer may be formed by controlling growth of the GaAs layer using MOCVD.
However, it is yet impossible to integrate the Ge material and the Group III-V compound semi-conductor material on a same Si substrate while implementing CMOS functions. Currently, a solution approaching this object is a prototype Ge-based CMOS device which integrates an nMOSFET and a pMOSFET by bonding an InGaAs channel to a Ge substrate (M. Yokoyama et al, Appl. Phys. Express 5, 076501, 2012). Another solution for integrating a Group III-V n-type channel and a Ge p-type channel is to utilize Si-based selective epitaxial growth. However, the quality of the Group III-V or Ge material obtained by the selective epitaxial growth, size of which is in the order of micrometers, is not ideal. Thus, the viability of the solution is yet to be determined. Also, tiny-size selective epitaxial growth employing high ART is getting a lot of attentions recently (J. S. Park et al, Appl. Phys. Lett. 90, 052113, 2007). An epitaxial material in a SiO2 trench is grown along a crystal plane consisting of {311} and {111} crystal planes (in parallel with the direction of the trench). Defects, such as mismatch dislocations, etc., at a Si—Ge interface generally extend along a growth direction of the epitaxial layer. As such, the mismatch dislocations are blocked by a SiO2 wall and thus cannot extend to a top layer. However, integration of the Si-based high-mobility N and P channels cannot be implemented by such a solution.
The method of the present invention utilizes UHVCVD in forming transition from the Si substrate to the Ge layer, and eliminates 4% strain by relaxed Ge at a bottom layer. Since the lattice mismatch between GaAs and Ge is only 800 ppm, generation of the mismatch dislocations between the Ge layer and the GaAs layer can be reduced. The problems related to the APDs and defects may be solved by combination of high- and low-temperature GaAs layers. Additionally, selective etching and ART epitaxial growth of Ge material are used in order to integrate the high-mobility Group III-V semiconductor and the Ge region on the Si substrate. Then a source-drain-gate process may be used to finally implement integration of the high-mobility InGaAs n-type channel and the Ge p-type channel on the Si substrate.